Stash is a mechanism that uses the core information carried by the ARM AXI bus to access the L3 cache. The CPU and I/O subsystems can access the L3 cache consistently by enabling stash, so the performance can be improved. Lang Cheng (3): RDMA/hns: Add support for CQ stash RDMA/hns: Add new interfaces to set/clear/read fields in QPC RDMA/hns: Add support for QP stash drivers/infiniband/hw/hns/hns_roce_common.h | 26 ++++++++++++++++++++++++++ drivers/infiniband/hw/hns/hns_roce_device.h | 1 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 9 +++++++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 5 +++++ 4 files changed, 41 insertions(+) -- 2.8.1
