On Wed, Mar 01, 2017 at 10:55:21AM -0700, Jason Gunthorpe wrote: > On Wed, Mar 01, 2017 at 11:29:20AM -0600, Shiraz Saleem wrote: > > > Is there DMA occuring to shadow_area? The shadow area contains status variables which are read by SW and updated by PCI device. > > Is this trying to implement CPU atomics in shadow_area for SMP? No. > What can wrong if it executes like this? > > get_64bit_val(qp->shadow_area, I40IW_BYTE_0, &temp); > udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ > set_64bit_val(wqe, I40IW_BYTE_24, header); > udma_to_device_barrier(); We need strict ordering that ensures write of the WQE completes before read of the shadow area. This ensures the value read from the shadow can be used to determine if a DB ring is needed. If the shadow area is read first, the algorithm, in certain cases, would not ring the DB when it should and the HW may go idle with work requests posted. > Is this the only barrier you are worried about? > Are the other changes OK? This is of most concern. The other changes look ok. Being reviewed. -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
