Re: [RFC PATCH] pci: pci-mvebu: setup BAR0 to internal-regs

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Hi Thomas,

On 6/8/20 10:43 PM, Thomas Petazzoni wrote:
> Some Armada 370/XP platforms really do use 0xd0000000 as the base
> address of the internal registers. This information is available in the
> DT. I think you could simply take the base address of the PCIe
> controller, round down to 1 MB (which is the size of the internal
> registers window) and that would give you the right address.

Apparently, the PCIe controller is outside of the internal registers space.

I could try to use a similar code as in
arch/arm/mach-mvebu/pm.c:mvebu_internal_reg_base or get the first child
of "internal-regs" and call of_translate_address on it with one zero cell.

Do you have a better solution?

Thanks,

-- 
- Shmuel Hazan

mailto:sh@xxxxxxxxxx | tel:+972-523-746-435 | http://tkos.co.il




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