Hi Thomas, On 6/10/20 1:27 PM, Thomas Petazzoni wrote: > Hello, > > On Tue, 9 Jun 2020 14:21:07 +0300 > "Shmuel H." <sh@xxxxxxxxxx> wrote: > >> Unfortunately, there is almost no documentation about the purpose of >> this register apart from this cryptic sentence: >> >> "BAR0 is dedicated to internal register access" (Marvell a38x >> functional docs, section 19.8). >> >> I can only assume that only specific devices trigger the need for the >> PCIe controller to access the SoC's internal registers and therefore >> will fail to operate properly. > In fact, section 10.2.6 of the Armada XP datasheet, about MSI/MSI-X > support gives a hint: in order for the device to do a write to the MSI > doorbell address, it needs to write to a register in the "internal > registers" space". So it makes a lot of sense that this BAR0 has to be > configured. > > Could you try to boot your system without your patch, and with the > pci=nomsi argument on the kernel command line ? This will prevent the > driver from using MSI, so it should fallback to legacy IRQs. If that > works, then we have the confirmation the issue is MSI related. This > will be useful just to have a good commit message that explains the > problem, because otherwise I am fine with your patch. I can confirm that pci=nomsi seems to solve the issue. The wil6210 operates and loads properly (without my patch), nice catch. I will send an updated patch shortly. Thanks! -- - Shmuel Hazan mailto:sh@xxxxxxxxxx | tel:+972-523-746-435 | http://tkos.co.il
