On Wed, 10 Jun 2020 17:17:15 +0300
"Shmuel H." <sh@xxxxxxxxxx> wrote:
> Apparently, the PCIe controller is outside of the internal registers space.
No, it is not.
It is outside of the internal-regs node in the DT because it needs more
"ranges" properties, but the PCIe controller registers *are* within the
internal registers window:
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
> I could try to use a similar code as in
> arch/arm/mach-mvebu/pm.c:mvebu_internal_reg_base or get the first child
> of "internal-regs" and call of_translate_address on it with one zero cell.
>
> Do you have a better solution?
In mvebu_pcie_map_registers(), we retrieve the address of the PCIe
registers for each port. You can take regs.start, round it down to 1
MB, and you'll get your base address.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
