Re: [PATCH v4 2/2] PCI: rcar: Fix missing MACCTLR register setting in initialize sequence

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On Tue, Nov 12, 2019 at 11:46:42AM +0100, Geert Uytterhoeven wrote:
> Hi Lorenzo,
> 
> On Tue, Nov 12, 2019 at 11:27 AM Lorenzo Pieralisi
> <lorenzo.pieralisi@xxxxxxx> wrote:
> > On Tue, Nov 12, 2019 at 01:48:03AM +0000, Yoshihiro Shimoda wrote:
> > > I'm sorry. I think I should not drop a sentence "because the bit 0 is
> > > set to 1 on reset" which has the reverted patch from this version. Also,
> > > the note seems to be difficult to understand. So, I'll rewrite this log
> > > like below. Is it acceptable?
> > >
> > > ---
> > > According to the R-Car Gen2/3 manual,
> >
> > Is this a publicly available manual ? If yes we provide a link, if
> > not I will reword the sentence below.
> 
> The same hardware block is present in the RZ/G series, and documented
> in RZ/G Series User's Manual: Hardware
> https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg1m.html#documents
> Chapter 39 ("PCIEC").
> Section 39.28.98 ("MAC Control Register (MACCTLR)")
> Section 39.3.1 ("Initialization"), Paragraph 3 ("Initial Setting of
> PCI Express").
> 
> Thanks, and happy digesting ;-)

Thank you, updated commit log and pushed out, pci/rcar branch.

Thanks,
Lorenzo



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