Never ever add stable@xxxxxxxxxxxxxxx in the CC list of the email
header. You should add the tag in the commit log as you did but
never CC stable when sending the patch email.
On Tue, Nov 05, 2019 at 07:51:29PM +0900, Yoshihiro Shimoda wrote:
> According to the R-Car Gen2/3 manual, "Be sure to write the initial
> value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT".
> To avoid unexpected behaviors, this patch fixes it. Note that
> the SPCHG bit of MACCTLR register description said "Only writing 1
> is valid and writing 0 is invalid" but this "invalid" means
> "ignored", not "prohibited". So, any documentation conflict doesn't
> exist about writing the MACCTLR register.
I am sorry but I don't understand what you mean, if either you or
any rcar maintainer can help me rewrite this log I will merge this
patch then, appreciated.
Thanks,
Lorenzo
> Reported-by: Eugeniu Rosca <erosca@xxxxxxxxxxxxxx>
> Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver")
> Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()")
> Cc: <stable@xxxxxxxxxxxxxxx> # v5.2+
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> drivers/pci/controller/pcie-rcar.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
> index 40d8c54..94ba4fe 100644
> --- a/drivers/pci/controller/pcie-rcar.c
> +++ b/drivers/pci/controller/pcie-rcar.c
> @@ -91,8 +91,11 @@
> #define LINK_SPEED_2_5GTS (1 << 16)
> #define LINK_SPEED_5_0GTS (2 << 16)
> #define MACCTLR 0x011058
> +#define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */
> #define SPEED_CHANGE BIT(24)
> #define SCRAMBLE_DISABLE BIT(27)
> +#define LTSMDIS BIT(31)
> +#define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
> #define PMSR 0x01105c
> #define MACS2R 0x011078
> #define MACCGSPSETR 0x011084
> @@ -613,6 +616,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
> if (IS_ENABLED(CONFIG_PCI_MSI))
> rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
>
> + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
> +
> /* Finish initialization - establish a PCI Express link */
> rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
>
> @@ -1235,6 +1240,7 @@ static int rcar_pcie_resume_noirq(struct device *dev)
> return 0;
>
> /* Re-establish the PCIe link */
> + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
> rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
> return rcar_pcie_wait_for_dl(pcie);
> }
> --
> 2.7.4
>
