On Thu, Nov 07, 2019 at 04:02:59PM +0200, Mika Westerberg wrote: > On Thu, Nov 07, 2019 at 07:52:46AM -0600, Bjorn Helgaas wrote: > > > > What would happen if a device below one of the non-hotplug > > > > bridges, e.g., 3a:00.0, had an I/O BAR? Would this patch > > > > still work? > > > > > > I think it would still work because now we call > > > pci_bus_size_bridges() only for non-hotplug bridge which do not > > > have I/O window open so pbus_size_io() fails to find the "free" > > > I/O resource on that bus and the kernel then fails to assign > > > that I/O resource for the device. > > > > Not sure I understand; are you saying that we wouldn't have the > > EC/GPE issue, but we'd be unable to use a device below 3a:00.0 > > that happened to have an I/O BAR? > > Yes. > > > That doesn't sound optimal because there is I/O space available > > that could be routed to 3a:00.0 > > If the none of the upstream bridges up to the PCIe root port does > not have I/O window open, I don't think we can do much about it. > Unless I'm missing something of course. The path to this hypothetical 3a:00.0 device is: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] 00:1b.0: Root Port to [bus 02-3a] 02:00.0: Switch Upstream Port to [bus 03-3a] 03:02.0: Switch Downstream Port to [bus 3a] 3a:00.0: reg 0x10: [io 0x????-0x????] None of the bridges (00:1b.0, 02:00.0, 03:02.0) currently has an open I/O window, but there's space available on bus 00 and windows *could* be opened. I guess it comes down to that ordering problem: this Notify() and acpiphp_native_scan_bridge() happens before pnp/system.c reserves things, so we don't yet know what space is actually available. If firmware had configured I/O windows for these bridges, 3a:00.0 would probably work. But it doesn't seem right that we would depend on that firmware configuration. Bjorn
