On 1/23/2019 12:54 PM, Lukas Wunner wrote: > <snip > > So I don't see a perfect solution. What device are we talking about > anyway? 400 ms is a *long* time. Some people have slow hands :-). This is a U.2 device. There are 2 pins (Pin 4 = IfDet#/Pin 10 = PRSNT#) that determine presence and each pin is a different length (On insert, IfDet# mates first, PRSNT# mates second, PCIe data lanes mate 3rd). SAS drive: IfDet# = 0, PRSNT# = 0 NVMe drive: IfDet# = 0, PRSNT# = 1. These 2 pins determine if it is a SAS or NVMe drive. We have to wait until both pins mate in order to know for sure it's an NVMe drive and therefore generate PRSNT# to DSP above the drive. But there is no way to know when both pins have mated due to the way the U.2 connector signals were defined so we have to dead wait. The time delta between these 2 pins mating on insert can vary substantially with different users. The time delta between these 2 pins mating for some users we measured was > 100 ms (others were less than 10 ms). That was for "normal" insert. It takes much longer if user intentionally tries to insert slowly. We chose 500 ms as the delay after P4 (IfDet#) mates before sampling the P10 (PRSNT#). About 100 ms of that is chewed up by the time delta of presence pins mating and PCIe data lanes mating plus the time to train the link leaving around 400 ms of time between DLLSC interrupt and PDSC interrupt. For future, we will hide the U.2 device from OS for 1 second after insert to all device to be fully inserted (in most cases) and reach steady state. New form factors will (hopefully) have presence pins that are last-to-mate so platforms/OSes do not have to rely on such guesswork to know when devices are fully inserted. > > Thanks, > > Lukas >
