On Mon, Aug 06, 2018 at 12:49:04PM -0400, Sinan Kaya wrote: > On 8/6/2018 12:44 PM, Lukas Wunner wrote: > >On Mon, Aug 06, 2018 at 11:06:48AM -0400, Sinan Kaya wrote: > >>Surprise Link Down is also a fatal error. > > > >Seriously? On a Downstream Port which has the Hot-Plug Surprise bit > >in the Slot Capabilities register set, Surprise Link Down is a fatal > >error? That would seem somewhat contradictory. Do you have a > >section number in the PCIe Base Spec for this? > > Spec 3.0. 7.10.2. Uncorrectable Error Status Register (Offset 04h) > bit 5 Surprise Down Error Status (Optional). Okay, thanks. Can we always mask out this bit on a hotplug port with surprise removal capability? Doesn't make sense to me to let AER/DPC spring to action in that case. Lukas
