From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
Now, the dw_pcie_setup_rc() works well, so remove the obsolete fixups:
Remove the Class field fix code from layerscape pcie driver.
Remove the line to enable write permission of DBI RO register from
artpec6 pcie driver.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
---
V4:
- Drop the change for qcom pcie driver's fixup
drivers/pci/dwc/pci-layerscape.c | 9 ---------
drivers/pci/dwc/pcie-artpec6.c | 6 ------
2 files changed, 15 deletions(-)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 0c1330fce01d..d22ed57dcc6f 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -73,14 +73,6 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
}
-/* Fix class value */
-static void ls_pcie_fix_class(struct ls_pcie *pcie)
-{
- struct dw_pcie *pci = pcie->pci;
-
- iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
-}
-
/* Drop MSG TLP except for Vendor MSG */
static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
{
@@ -145,7 +137,6 @@ static int ls_pcie_host_init(struct pcie_port *pp)
ls_pcie_disable_outbound_atus(pcie);
dw_pcie_dbi_ro_wr_en(pci);
- ls_pcie_fix_class(pcie);
ls_pcie_clear_multifunction(pcie);
dw_pcie_dbi_ro_wr_dis(pci);
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 5d81f1d884e3..d153491f600f 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -141,12 +141,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
usleep_range(100, 200);
- /*
- * Enable writing to config regs. This is required as the Synopsys
- * driver changes the class code. That register needs DBI write enable.
- */
- dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
-
/* setup root complex */
dw_pcie_setup_rc(pp);
--
2.14.1
