Às 9:23 AM de 8/3/2017, Zhiqiang Hou escreveu: > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > > The existing fix doesn't actually work because the Class register is > read-only, so it must enable the write permission before write the > correct value to this register. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > --- > V2: > - None > > drivers/pci/dwc/pcie-designware-host.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c > index d29c020..6e10cda 100644 > --- a/drivers/pci/dwc/pcie-designware-host.c > +++ b/drivers/pci/dwc/pcie-designware-host.c > @@ -634,8 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); > > + /* Enable write permission for the DBI read-only register */ > + dw_pcie_dbi_ro_wr_en(pci); > /* program correct class for RC */ > dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); > + /* Better disable write permission right after the update */ > + dw_pcie_dbi_ro_wr_dis(pci); > > dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); > val |= PORT_LOGIC_SPEED_CHANGE; > Acked-By: Joao Pinto <jpinto@xxxxxxxxxxxx>
