Às 9:23 AM de 8/3/2017, Zhiqiang Hou escreveu:
> From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
>
> Use the accessors instead accessing the DBI read-only write enable
> register directly. And the STRFMR1 is not read-only register, so move it
> out from the write-enable bracket.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> ---
> V2:
> - New patch split from patch v1 3/3.
>
> drivers/pci/dwc/pci-layerscape.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index fd86128..09056a6 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -33,7 +33,6 @@
>
> /* PEX Internal Configuration Registers */
> #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
> -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
>
> struct ls_pcie_drvdata {
> u32 lut_offset;
> @@ -155,11 +154,12 @@ static void ls_pcie_host_init(struct pcie_port *pp)
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct ls_pcie *pcie = to_ls_pcie(pci);
>
> - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> + dw_pcie_dbi_ro_wr_en(pci);
> ls_pcie_fix_class(pcie);
> ls_pcie_clear_multifunction(pcie);
> + dw_pcie_dbi_ro_wr_dis(pci);
> +
> ls_pcie_drop_msg_tlp(pcie);
> - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> }
>
> static int ls_pcie_msi_host_init(struct pcie_port *pp,
>
Acked-By: Joao Pinto <jpinto@xxxxxxxxxxxx>
