On Monday 18 November 2013, Kishon Vijay Abraham I wrote: > commit b91b61d594f293d994d87f10eb8a1a3b2e5f8977 > Author: Kishon Vijay Abraham I <kishon@xxxxxx> > Date: Wed Oct 30 14:51:58 2013 +0530 > > pci: host: pcie-designware: Use *base-mask* for configuring the iATU > > In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit > address. So whenever the cpu issues a read/write request, the 4 most > significant bits are used by L3 to determine the target controller. > For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe controller but > the PCIe controller will see only (0x000_0000 - 0xFFF_FFF). So for programming > the outbound translation window the base should be programmed as 0x000_0000. > Whenever we try to write to say 0x2000_0000, it will be translated to whatever > we have programmed in the translation window with base as 0x000_0000. > > Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx> Sorry I didn't see that patch earlier. Have you had a look at the definition of the "dma-ranges" property? I think that is something we have already defined that can handle this in a more generic way. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
