Hi, Currently I see in pcie-designware.c we use only 2 ATU regions. We re-use INDEX0 for mem outbound and cfg0, and INDEX1 for cfg1 and io. So I'd like to know if in your platform, do you have only 2 address translation regions? In DRA7xx we have 16 outbound regions and 4 inbound regions. Also the same designware IP can be used as a EP also no? Shouldn't we move it out of drivers/pci/host and allow it to be configured as EP also? Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
