Hi, > + Marek, Tim, arnd > > Hi Kishon, > > On Wed, Oct 23, 2013 at 11:45:34PM +0800, Kishon Vijay Abraham I wrote: > > Hi Pratyush, > > > > On Wednesday 23 October 2013 10:06 AM, Pratyush Anand wrote: > > > Hi Kishon, > > > > > > On Tue, Oct 22, 2013 at 10:20:01PM +0800, Kishon Vijay Abraham I wrote: > > >> Hi Pratyush, Jingoo, > > >> > > >> On Tuesday 22 October 2013 10:46 AM, Jingoo Han wrote: > > >>> On Monday, October 21, 2013 10:28 PM, Kishon Vijay Abraham I wrote: > > >>>> Currently I see in pcie-designware.c we use only 2 ATU regions. We > > >>>> re-use INDEX0 for mem outbound and cfg0, and INDEX1 for cfg1 and > > >>>> io. So I'd like to know if in your platform, do you have only 2 > > >>>> address translation regions? In DRA7xx we have 16 outbound regions > > >>>> and 4 inbound regions. > > >>> > > >>> In Exynos, there are only 2 inbound and 2 outbound viewpoints. Jumping in a tad late, MX6 has 4 inbound and 4 outbound according to MX6DQRM Rev. 1, 04/2013 sections: - 48.3.9.1.1 (bullet 8) - 48.3.9.1.2 (bullet 7) - 48.10.42 (Region_Index description in the table PCIE_PL_iATUVR) Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
