On Wed, Sep 18, 2024 at 4:13 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> wrote: > > Add support for restricting the port's link width by specifying > the num-lanes devicetree property in the PCIe node. > > The setting is done in the GEN_SETTINGS register (in the driver > named as PCIE_SETTING_REG), where each set bit in [11:8] activates > a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2). > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> Reviewed-by: Fei Shao <fshao@xxxxxxxxxxxx>
