This series adds support for limiting the PCI-Express link speed (or PCIe gen restriction) and link width (number of lanes) in the pcie-mediatek-gen3 driver. The maximum supported pcie gen is read from the controller itself, so defining a max gen through platform data for each SoC is avoided. Both are done by adding support for the standard devicetree properties `max-link-speed` and `num-lanes`. Please note that changing the bindings is not required, as those do already allow specifying those properties for this controller. AngeloGioacchino Del Regno (2): PCI: mediatek-gen3: Add support for setting max-link-speed limit PCI: mediatek-gen3: Add support for restricting link width drivers/pci/controller/pcie-mediatek-gen3.c | 76 ++++++++++++++++++++- 1 file changed, 74 insertions(+), 2 deletions(-) -- 2.45.2
