Re: [PATCH v2 2/3] PCI: Create new reset method to force SBR for CXL

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       For T2 and T3 persistent memory devices, wouldn’t we also need a way to trigger device cache flush and then disable out of cxl_reest_bus_function()?
       CXL Spec 3.1 (Aug ’23), Section 9.3 which refers to system reset flow has RESETPREP VDMs to trigger device cache flush, put memory in safe state, etc. These devices would benefit from this in case of SBR as well, but it is root port specific so may be an ACPI method could be involved out of cxl_reset_bus_function()?


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