[add Davidlohr] On Wed 08-05-24 18:35:50, Adam Manzanares wrote: > On Tue, May 07, 2024 at 01:48:46PM +0200, Michal Hocko wrote: > > On Mon 06-05-24 19:27:10, Adam Manzanares wrote: > > > Hello all, > > > > > > I would like to have a discussion with the CXL development community about > > > current outstanding issues and also invite developers interested in RAS and > > > memory tiering to participate. > > > > > > The first topic I believe we should discuss is how we can ensure as a group > > > that we are prioritizing upstream work. On a recent upstream CXL development > > > discussion call there was a call to review more work. I apologize for not > > > grabbing the link, but I believe Dave Jiang is leveraging patchwork and this > > > link should be shared with others so we can help get more reviews where needed. > > > > > > The second topic I would like to discuss is how we integrate RAS features that > > > have similar equivalents in the kernel. A CXL device can provide info about > > > memory media errors in a similar fashion to memory controllers that have EDAC > > > support. Discussions have been put on the list and I would like to hear thoughts > > > from the community about where this should go [1]. On the same topic CXL has > > > port level RAS features and the PCIe DW series touched on this issue [2] > > > > > > The third topic I would like to discuss is how we can get a set of common > > > benchmarks for memory tiering evaluations. Our team has done some initial > > > work in this space, but we want to hear more from end users about their > > > workloads of concern. There was a proposal related to this topic, but from what > > > I understand no meeting has been held [3]. > > > > > > The last topic that I believe is worth discussion is how do we come up with > > > a baseline for testing. I am aware of 3 efforts that could be used cxl_test, > > > qemu, and uunit testing framework [4]. > > > > This seems to be quite a lot for a single time slot. I think it would > > make sense to split that into more slots. WDYT? > > +1. I think the performance implications of CXL memory and how it relates > to existing memory management code tackling performance differentiated memory > would be nice to separate. I think Davidlohr would be a great candidate to > lead this discussion. WDYT Davidlohr? -- Michal Hocko SUSE Labs
