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On 14/04/12 18:37, Steven Newbury wrote:
> On 12/04/12 17:40, Steven Newbury wrote:
>> On Thu, 12 Apr 2012, 17:07:33 BST, Yinghai Lu
>> <yinghai@xxxxxxxxxx> wrote:
>
>>> On Thu, Apr 12, 2012 at 4:22 AM, Steven Newbury
>>> <steve@xxxxxxxxxxxxxxx> wrote:
>>>> Thanks, that fixed it! :) I had a similar patch I've been
>>>> working on but I had my fix in the wrong place!
>>>>
>>>> In the working case, initially the BIOS has set GMA to
>>>> within the low system DRAM 0xC0000000 obviously invalid.
>>>> This conflict is detected and it's relallocated to
>>>> 0x12000000.
>>>>
>>>> I've attempted to modify probe.c to disable 64-bit BARs not
>>>> allocated above 4G so they get reallocated above when
>>>> possible later. It seemed to work, but again broke GMA
>>>> despite the BAR originally containing an invalid address as
>>>> mentioned above, it seems for some reason something is
>>>> different when the conflict is detected and rellocated,
>>>> compared to disabling it early then allocating a valid
>>>> value..?
>>>>
> I've created a new quirk utilising an extra PCI resource flag to
> force reallocation of the resource. It's the first approach I've
> had any success at. It does work. Only "Intel Page Flush" now
> gets allocated @0xe0000000!
>
>
Hopefully this should fix "Intel Flush Page"
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commit ccc1099a1474815f4094e8689ca0b518de464230
Author: Steven Newbury <steve@xxxxxxxxxxxxxxx>
Date: Sat Apr 14 19:02:47 2012 +0100
intel-gtt: Use pci_bus_alloc_resource_fit() to allocate "Intel Flush Page".
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 77e150e..30b1ea2 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1036,9 +1036,9 @@ static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
static int intel_alloc_chipset_flush_resource(void)
{
int ret;
- ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
+ ret = pci_bus_alloc_resource_fit(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
- pcibios_align_resource, intel_private.bridge_dev);
+ pcibios_align_resource, intel_private.bridge_dev, 1);
return ret;
}
