Re: Change BAR size at resource allocation

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On Thu, Apr 28, 2011 at 2:51 PM, Matthew Wilcox <matthew@xxxxxx> wrote:
> On Wed, Apr 27, 2011 at 11:25:02PM -0500, Xianghua Xiao wrote:
>> I have a few large BARs from various PCI/PCIe devices and they
>> exceeded my linear PCI mapping space on the ARM chip. The chip can
>> only do 256MB mapping at the same time. I need map all devices at the
>> same time so I can only assign a portion of certain large BARs, e.g
>>
>> DeviceX: BAR0=512MB Â--> only assigned 8M resource to it
>> ...
>> DeviceY: BAR2=512MB Â--->only assigned 16M resource to it
>>
>> BAR sizes are provided by hardware and they're read-only. ÂI think the
>> above map should not cause trouble, correct? DeviceX/DeviceY will use
>> the 8M/16M window to address its whole 512M for inbound transaction
>> without problems here. I'm hacking pci_read_base to decrease the size.
>
> You can't do that. ÂThe low N bits of a BAR are forced to be zero.
> So while you might try to assign an 8MB address to a 512MB BAR, the device
> is still going to decode the entire 512MB range that it's placed in.
That's exactly what I am worrying about.
>
> What you might be able to do is program the bridge of the upstream PCI
> bridge to forward on a smaller range. ÂBut if you've got two devices
> with 512MB BARs on the same PCI bus, you won't be able to do this either.
>
> PCI has a resizable BAR capability ... I presume the devices you're
> using don't support this.
I don't believe we can support that.
>
> I think you're trying to do something that your hardware doesn't support.
> Might I invite you to try using a processor with a larger address space?
> :-)
Yes somebody else made that decision, sigh.
Thanks a lot!
>
> --
> Matthew Wilcox             ÂIntel Open Source Technology Centre
> "Bill, look, we understand that you're interested in selling us this
> operating system, but compare it to ours. ÂWe can't possibly take such
> a retrograde step."
>
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