On Wed, Apr 27, 2011 at 11:25:02PM -0500, Xianghua Xiao wrote: > I have a few large BARs from various PCI/PCIe devices and they > exceeded my linear PCI mapping space on the ARM chip. The chip can > only do 256MB mapping at the same time. I need map all devices at the > same time so I can only assign a portion of certain large BARs, e.g > > DeviceX: BAR0=512MB --> only assigned 8M resource to it > ... > DeviceY: BAR2=512MB --->only assigned 16M resource to it > > BAR sizes are provided by hardware and they're read-only. I think the > above map should not cause trouble, correct? DeviceX/DeviceY will use > the 8M/16M window to address its whole 512M for inbound transaction > without problems here. I'm hacking pci_read_base to decrease the size. You can't do that. The low N bits of a BAR are forced to be zero. So while you might try to assign an 8MB address to a 512MB BAR, the device is still going to decode the entire 512MB range that it's placed in. What you might be able to do is program the bridge of the upstream PCI bridge to forward on a smaller range. But if you've got two devices with 512MB BARs on the same PCI bus, you won't be able to do this either. PCI has a resizable BAR capability ... I presume the devices you're using don't support this. I think you're trying to do something that your hardware doesn't support. Might I invite you to try using a processor with a larger address space? :-) -- Matthew Wilcox Intel Open Source Technology Centre "Bill, look, we understand that you're interested in selling us this operating system, but compare it to ours. We can't possibly take such a retrograde step." -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
