On Tue, Jan 20, 2009 at 7:39 PM, Mark Lord <liml@xxxxxx> wrote: ... > Next.. who knows something about debugging MSI across PCI bridges ? > I've got a 64-bit box here, PCIe near the core, but with full PCI-X > slots on the far side of two bridges. > > The kernel happily allows my driver to setup MSI, but the interrupts > never arrive. So something somewhere in between is either > > (1) not set up or quirked quite right, or > (2) one of the bridges won't pass MSI and we don't detect that. > > I'll poke more at it later and post some info, if somebody out there > knows enough about this kind of thing to provide some basic hints. Basic Hints: 1) post lspci -v output to verify device (and bridges) is programmed correctly. 2) look for chipset quirks that disable global msi 3) Make sure MMIO ranges for 0xfee00000 are routed to local APIC ie each bridge needs to route that address somehow (negative decode is common for upstream). 4) manually trigger the MSI by doing a MMIO write to the correct 0xfee00000 address with the assigned vector in order to see if your interrupt handler gets called. After that, it's about collecting PCI-X or PCIe traces to verify the device is generating the transactions correctly and the bridges are forwarding them. hth, grant -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
