On Fri, Dec 05, 2008 at 09:31:32AM +0530, Deepak Pandian wrote:
...
> > You can see the core kernel handling 64-bit BARs in drivers/pci/probe.c
> > in the __pci_read_base() function. In earlier kernels, this was found
> > in the pci_read_bases() function.
"Earlier kernels" means 2.6.26 and before.
2.6.27 and later
> > It handles both BARs located above
> > 4GB as well as BARs which map an area >4GB. There aren't many devices
> > which have such large address space requirements, so this code is probably
> > not well tested, but it should work.
> >
>
> In read_bases I see,
>
> else if (lhi) {
> /* 64-bit wide address, treat as disabled */
> pci_write_config_dword(dev, reg,
> l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
> pci_write_config_dword(dev, reg+4, 0);
> res->start = 0;
> res->end = sz;
> }
> Is there any specific reason for disabling it?
This is in the 32-bit build. The "#if BITS_PER_LONG == 64" is a test for
i386 (32-bit) and x86-64 builds. The struct resource definition used
to store the BAR values wasn't quite in line with the usage for this
kernel version:
#ifdef CONFIG_RESOURCES_64BIT
typedef u64 resource_size_t;
#else
typedef u32 resource_size_t;
#endif
I think drivers/pci code in 2.6.26 kernel should have used RESOURCES_64BIT
instead of BITS_PER_LONG.
Even though usage of RESOURCES_64BIT is inconsistent:
grundler@gsyprf3:/usr/src$ find linux-2.6.27.8 | fgrep -v arch/ | xargs fgrep CONFIG_RESOURCES_64BIT
linux-2.6.27.8/drivers/pci/setup-bus.c:#ifdef CONFIG_RESOURCES_64BIT
linux-2.6.27.8/include/linux/types.h:#ifdef CONFIG_RESOURCES_64BIT
It's always defined on x86 (both 32 and 64-bit kernel builds).
The code in __pci_read_bases() looks right to me:
if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
dev_err(&dev->dev, "can't handle 64-bit BAR\n");
goto fail;
} else ...
> I can fix pci related
> stuff but I am not sure whether alloc resource can handle resource
> with width greater than 4 GB.?
In general, I agree with willy. However, odds are good you'll
probably need to fix a few more minor nits like this one.
Note that I've ONLY tested > 4GB BARs on ia64 (itanium) kernel builds.
I don't recall if we ever used any PCI MMIO ranges on 64-bit PARISC machines.
> Thanks for your interest.
hth,
grant
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