Hi Mathew,
On Fri, Dec 5, 2008 at 12:15 AM, Matthew Wilcox <matthew@xxxxxx> wrote:
> On Fri, Dec 05, 2008 at 12:09:40AM +0530, Deepak Pandian wrote:
>> Hi,
>>
>> In ppc4xx_pci i see the pci size to be declared as
>> u32 lah, lal, pciah, pcial, sa;
>>
>> Also at many other places I see the pci region is not capable of
>> handling resources > 4GB. I am planning to work on this arch specific
>> code to make it handle pci resource of width greater than 4 GB.
>>
>> But before that i wanted to clarify whether the core kernel will be
>> able to handle pci regions with width greater than 4GB.
>
> You can see the core kernel handling 64-bit BARs in drivers/pci/probe.c
> in the __pci_read_base() function. In earlier kernels, this was found
> in the pci_read_bases() function. It handles both BARs located above
> 4GB as well as BARs which map an area >4GB. There aren't many devices
> which have such large address space requirements, so this code is probably
> not well tested, but it should work.
>
In read_bases I see,
else if (lhi) {
/* 64-bit wide address, treat as disabled */
pci_write_config_dword(dev, reg,
l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
pci_write_config_dword(dev, reg+4, 0);
res->start = 0;
res->end = sz;
}
Is there any specific reason for disabling it? I can fix pci related
stuff but I am not sure whether alloc resource can handle resource
with width greater than 4 GB.?
Thanks for your interest.
--
With Regards,
Deepak Pandian
"Time is precious,One day we will find that we have less than what we
think" -RandyPausch
www.peerlessdeepak.wordpress.com
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