On Fri, Dec 05, 2008 at 12:09:40AM +0530, Deepak Pandian wrote: > Hi, > > In ppc4xx_pci i see the pci size to be declared as > u32 lah, lal, pciah, pcial, sa; > > Also at many other places I see the pci region is not capable of > handling resources > 4GB. I am planning to work on this arch specific > code to make it handle pci resource of width greater than 4 GB. > > But before that i wanted to clarify whether the core kernel will be > able to handle pci regions with width greater than 4GB. You can see the core kernel handling 64-bit BARs in drivers/pci/probe.c in the __pci_read_base() function. In earlier kernels, this was found in the pci_read_bases() function. It handles both BARs located above 4GB as well as BARs which map an area >4GB. There aren't many devices which have such large address space requirements, so this code is probably not well tested, but it should work. -- Matthew Wilcox Intel Open Source Technology Centre "Bill, look, we understand that you're interested in selling us this operating system, but compare it to ours. We can't possibly take such a retrograde step." -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
