On Thu, 2024-07-25 at 19:46 +0200, Mikulas Patocka wrote: > > > On Thu, 25 Jul 2024, James Bottomley wrote: > > > > > #define ARCH_DMA_MINALIGN (128) > > > > #define ARCH_KMALLOC_MINALIGN (8) > > > > > > > > L1_CACHE_BYTES is 64 on arm64. > > > > > > > > Possibly, the same can occur on parisc. > > > > > > > > Dave > > > > > > L1_CACHE_BYTES is a performance hint that is used to avoid cache > > > line ping-pong when multiple CPUs modify nearby data. > > > > > > ARCH_DMA_MINALIGN is the biggest possible cache line size to > > > avoid DMA data corruption. As there are some arm64 machines with > > > 128-byte cache line, arm64 has to define it to 128. > > > > > > James said that the L2 cache on PA8800/8900 is coherent with PCI. > > > So, I think that ARCH_DMA_MINALIGN should be 64 (is that the L1 > > > cache line size on PA8800/8900?). > > > > By default, if unset, ARCH_DMA_MINALIGN defaults to alignof(long > > long), so it is already 64 on parisc. > > > > James > > No, alignof(long long) is 8 :-) Sorry, thinking in bits not bytes. We definitely need that to be at least 16 for all the pure VIPT systems. James
