Hi Thanks for fixing the cache aliasing issues on PA-RISC in the commit 72d95924ee35c8cd16ef52f912483ee938a34d49. I think there is still one problem left - and that is ARCH_DMA_MINALIGN. Currently, it is 16, which is obviously wrong. Some comments in the kernel say that PA8900 has L2 cache with 128-byte line size, so I think that ARCH_DMA_MINALIGN should be 128 as well. The question is - can the CPU speculatively mark a cache line as dirty and write it back? If yes, we have a big problem - Linux assumes that a part of the page may be used for DMA transfer and another part of that page may be used for normal cacheable structures. If the PA-RISC CPU speculatively prefetched and wrote back a cache line, it could corrupt the DMA transfer. If the CPU doesn't speculatively mark cache lines as dirty, then increasing ARCH_DMA_MINALIGN would be sufficient solution. Mikulas
