On 2019-05-28 1:39 p.m., Sven Schnelle wrote: > Hi, > > On Tue, May 28, 2019 at 07:24:29PM +0200, Rolf Eike Beer wrote: >> Am Dienstag, 28. Mai 2019, 19:06:48 CEST schrieb John David Anglin: >>> On 2019-05-28 11:38 a.m., Sven Schnelle wrote: >>>> Interesting. Now that you mention it i see that my C3750 reports the same. >>>> Google returned the following page >>>> https://support.hpe.com/hpsc/swd/public/detail?swItemId=PF_CCJ70020 >>>> >>>> Which is 2.0, and only mentions "C3650/C3700/C3750/J6700/J6750 firmware" >>>> So maybe these machines have NP set, and machines "below" (like C3600) >>>> don't have it set. >>>> >>>> I wonder what happens if you try to flash a 5.0 firmware to such a box. >>> >>> From what I see, the "C3650/C3700/C3750/J6700/J6750" and "HP 9000 Model >>> B1000/C3000/J5000/J7000" use different firmware. >> >> Which makes sense as the former have use a 8600 CPU, while the latter have >> 8700 ones. > > Exactly. And as: > > a) All C3600 PDC versions clear the NP bit > b) All C37XX/J5000 PDC version set the NP bit > > i don't think there's some bug in the PDC. I would guess that the patch Carlo > reported to fix issues is just hiding the real problem. Would be interesting > to run Carlo's Test on a C37XX. Probably, hardware cache coherent I/O is not implemented correctly for Elroy based systems. https://www.hpl.hp.com/hpjournal/96feb/feb96a6.pdf Does it work on C360? Dave -- John David Anglin dave.anglin@xxxxxxxx
