On 05.01.19 00:21, Dennis Clarke wrote: > On 1/4/19 6:05 PM, Helge Deller wrote: >> On parisc, each IRQ can only be handled by one CPU, and currently CPU0 >> is choosen as default for handling all IRQs by default. >> With this patch we now assign each requested IRQ to one of the online >> CPUs (and thus distribute the IRQs across all CPUs), even without an >> instance of irqbalance running. > > Will this take into consideration the features in default_smp_affinity > and allow processor cores to be considered 'non interrupt' service > state? It seems the feature of default_smp_affinity to disable specific cores from servicing interrupts doesn't work on the parisc platform. On a 2-CPU machine I booted with the "irqaffinity=0" kernel commandline option (to enable CPU#0 and disable CPU#1), which then led to a hanging kernel when CPU#1 ist started. On parisc, each CPU needs to handle at least it's timer and IPMI interrupt. Any idea what I should try? Helge
