On 1/4/19 6:05 PM, Helge Deller wrote:
On parisc, each IRQ can only be handled by one CPU, and currently CPU0 is choosen as default for handling all IRQs by default. With this patch we now assign each requested IRQ to one of the online CPUs (and thus distribute the IRQs across all CPUs), even without an instance of irqbalance running.
Will this take into consideration the features in default_smp_affinity and allow processor cores to be considered 'non interrupt' service state? Dennis
