On 09/10/2013 03:19 PM, Tomi Valkeinen wrote:
On 10/09/13 15:12, Tero Kristo wrote:
If it claims it is not locked, it means the DPLL itself is disabled. You
could try clk_enable for the clock before doing clk_set_rate.
Hmm, so is it required to enable the clock before setting the rate? If
so, I think I'm using the clocks wrong in all the places =).
In generic case, it is not. But DPLLs behave strangely if they go to low
power stop mode. If there is any downstream clock enabled for a specific
DPLL it is enabled and things work okay.
One could also argue that the API behavior in OMAP is wrong currently,
as the bypass rate is something you are most likely never actually going
to use for anything....
Just try the change and check the results.
-Tero
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