On 10/09/13 15:12, Tero Kristo wrote: > If it claims it is not locked, it means the DPLL itself is disabled. You > could try clk_enable for the clock before doing clk_set_rate. Hmm, so is it required to enable the clock before setting the rate? If so, I think I'm using the clocks wrong in all the places =). Tomi
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