On 10.09.2013 14:12, Tero Kristo wrote:
>> I debugged this a bit and found that this issue (dpll4_m4x2_ck clock is
>> not 2 times dpll4_m4_ck) results from this code:
>>
>> arch/arm/mach-omap2/dpll3xxx.c:
>>
>> unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> ...
>> if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
>> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>> rate = parent_rate;
>> else
>> rate = parent_rate * 2;
>> return rate;
>> }
>>
>> As marked above, v is at that early time 0x1 (unmasked value of this
>> register is 0x38310037). So the DPLL4 is not locked but in low power top
>> mode (OMAP3XXX_EN_DPLL_LOCKED = 0x7).
>>
>> Any hint whats missing here?
>
> If it claims it is not locked, it means the DPLL itself is disabled. You
> could try clk_enable for the clock before doing clk_set_rate.
Yes, of course. This solves this issue. Thanks.
Tomi, most likely some clk_enable() / clk_disable() calls are missing
from the PM functions as well?
Cheers,
Stefan
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