Hi Will
On Sun, 28 Jul 2013, Will Deacon wrote:
> On Sun, Jul 28, 2013 at 06:43:24AM +0100, Paul Walmsley wrote:
> >
> > Commit 621a0147d5c921f4cc33636ccd0602ad5d7cbfbc ("ARM: 7757/1: mm:
> > don't flush icache in switch_mm with hardware broadcasting") breaks
> > the boot on OMAP2430SDP with omap2plus_defconfig. Tracked to an
> > undefined instruction abort from the CP15 read in
> > cache_ops_need_broadcast(). It turns out that early ARM1136 variants
> > don't support several CP15 registers that later ARM cores do.
> > ARM1136JF-S TRM section 3.2.1 "Register allocation" has the details.
>
> Intriguing... I wouldn't expect a cp15 read to be emitted for 1136, since
> the SMP_ON_UP magic should have caused is_smp() to return false.
>
...
> So we should have returned 0 here without exploding (this just reads a
> .globl initialised in head.S). Are we somehow misidentifying your 1136
> as an SMP core?
You're right - the is_arm1136_r0() logic is completely unnecessary - it's
just the 'asm volatile' that makes the difference.
- Paul
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