Commit 621a0147d5c921f4cc33636ccd0602ad5d7cbfbc ("ARM: 7757/1: mm:
don't flush icache in switch_mm with hardware broadcasting") breaks
the boot on OMAP2430SDP with omap2plus_defconfig. Tracked to an
undefined instruction abort from the CP15 read in
cache_ops_need_broadcast(). It turns out that early ARM1136 variants
don't support several CP15 registers that later ARM cores do.
ARM1136JF-S TRM section 3.2.1 "Register allocation" has the details.
So, prevent cache_ops_need_broadcast() from attempting the CP15 read
if the running CPU doesn't provide the register.
cache_ops_need_broadcast() is a hot path function, so focus on
minimizing the execution time impact. A subsequent patch will take
care of the remaining cases in the current kernel.
Thanks to Will Deacon for helping track this down.
Signed-off-by: Paul Walmsley <paul@xxxxxxxxx>
Cc: Will Deacon <will.deacon@xxxxxxx>
---
Intended for v3.11-rc.
Tested (along with the followup patch) here:
http://www.pwsan.com/omap/testlogs/bisect_2430sdp_hang_v3.11-rc/20130727224434/README.txt
against stock v3.11-rc2, so several boards aren't booting due to unrelated
issues.
arch/arm/include/asm/cputype.h | 37 ++++++++++++++++++++++++++++++++++++-
arch/arm/include/asm/smp_plat.h | 4 +++-
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 8c25dc4..91ccd77 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -76,6 +76,8 @@
#define ARM_CPU_XSCALE_ARCH_V2 0x4000
#define ARM_CPU_XSCALE_ARCH_V3 0x6000
+#define ARM_CPU_ARM1136R0 0x4107b360
+
extern unsigned int processor_id;
#ifdef CONFIG_CPU_CP15
@@ -89,10 +91,43 @@ extern unsigned int processor_id;
__val; \
})
+
+/* Workaround for missing CP15 registers on ARM1136 r0 */
+# if defined(CONFIG_CPU_V6)
+/**
+ * cpu_is_arm1136_r0 - is the kernel running on an ARM1136 r0 core?
+ *
+ * Returns true if the kernel is running on an ARM1136 r0 core, or
+ * false otherwise. Callers use this to avoid undefined instruction
+ * aborts from CP15 accesses to registers not present on the r0
+ * variant, or to detect whether certain CPU features are available.
+ * ARM1136JF-S TRM section 3.2.1 "Register allocation"
+ */
+static inline bool __attribute_const__ cpu_is_arm1136_r0(void)
+{
+ return ((read_cpuid(CPUID_ID) & 0xfffffff0) == ARM_CPU_ARM1136R0);
+}
+
+/*
+ * The mrc in the read_cpuid_ext macro must not be reordered on ARMv6,
+ * else the compiler may move it before any ARM1136r0 test.
+ */
+# define CPUID_EXT_REORDER volatile
+# else
+static inline bool __attribute_const__ cpu_is_arm1136_r0(void) { return false; }
+# define CPUID_EXT_REORDER
+# endif
+
+/*
+ * Early ARM1136 variants don't support many CP15 registers provided
+ * on later cores. Users of read_cpuid_ext must ensure that it won't
+ * be used unless it's known that the running core provides the CP15
+ * register ext_reg. See cpu_is_arm1136_r0() above.
+ */
#define read_cpuid_ext(ext_reg) \
({ \
unsigned int __val; \
- asm("mrc p15, 0, %0, c0, " ext_reg \
+ asm CPUID_EXT_REORDER("mrc p15, 0, %0, c0, " ext_reg \
: "=r" (__val) \
: \
: "cc"); \
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 6462a72..76214cb 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -25,7 +25,6 @@ static inline bool is_smp(void)
#endif
}
-/* all SMP configurations have the extended CPUID registers */
#ifndef CONFIG_MMU
#define tlb_ops_need_broadcast() 0
#else
@@ -43,6 +42,9 @@ static inline int tlb_ops_need_broadcast(void)
#else
static inline int cache_ops_need_broadcast(void)
{
+ if (cpu_is_arm1136_r0())
+ return 0;
+
if (!is_smp())
return 0;
--
1.8.3.2
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