On Tuesday 05 February 2013 03:04 PM, Roger Quadros wrote:
Hi Rajendra,
On 02/04/2013 05:58 PM, Roger Quadros wrote:
Provide the RESET and Power regulators for the USB PHY,
the USB Host port mode and the PHY device.
Also provide pin multiplexer information for the USB host
pins.
Signed-off-by: Roger Quadros <rogerq@xxxxxx>
---
arch/arm/boot/dts/omap4-panda.dts | 55 +++++++++++++++++++++++++++++++++++++
1 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 4122efe..fe2d3d4 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -57,6 +57,35 @@
"AFML", "Line In",
"AFMR", "Line In";
};
+
+ /* HS USB Port 1 RESET */
+ hsusb1_reset: hsusb1_reset_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb1_reset";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 30 0>; /* gpio_62 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ /* HS USB Port 1 Power */
+ hsusb1_power: hsusb1_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 1 0>; /* gpio_1 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 1 */
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ reset-supply = <&hsusb1_reset>;
+ vcc-supply = <&hsusb1_power>;
+ };
This is the patch I was discussing with you about before.
Let me explain the problem again.
The Pandaboard has a USB PHY whose reference clock is provided by
FREF_CLK3 pin which is a clock generated by the OMAP.
The PHY driver expects a reference to this clock in the PHY device node.
Well, the driver just does a clk_get(dev, "main_clk"); and clk_get() is
then able to either pick the reference from the PHY dt node or from a
clkdev entry.
The problem here seems to be that you are not able to add a clkdev entry
because the device name wouldn't be fixed, since you have a node in
the form of 'node: node {'. All other onchip OMAP devices don't have
this issue because they have an entry in the form of 'node: node@addr'
and hence have a fixed device name and hence can add a clkdev entry for
the clocks they want to control.
I don't know if there is any good way to define the DT node for the
on board PHY in such a way that the device name is always fixed, in
which case you can then add a clkdev entry for 'dev, main_clk' mapping
to the onchip clock that provides the clock, but if there is one, then
that should fix your problem.
See the above node hsusb1_phy. we would need something like
hsusb1_phy {
...
clocks = <&fref_clk3>;
clock-names = "main_clk";
...
};
Currently on OMAP, there is no way to provide a phandle to this clock.
Is it practical to provide device tree based implementation of at least
the externally accessible OMAP clocks?
cheers,
-roger
};
&omap4_pmx_core {
@@ -67,6 +96,7 @@
&mcbsp1_pins
&dss_hdmi_pins
&tpd12s015_pins
+ &hsusbb1_pins
>;
twl6040_pins: pinmux_twl6040_pins {
@@ -110,6 +140,23 @@
0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
>;
};
--
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