On 08/07/2012 02:10 PM, Tony Lindgren wrote:
> You need to also consider that CONTROL_DEVCONF0 has the MMC/SDIO module input
> clock selection. So pinctrl-single binding would have to be expanded to also
> support one-bit-per-mux type registers in addition to one-register-per-mux
> registers. And then this could also be used for the MMC/SDIO module input clock.
Or if the clock selection for MMC/SDIO also static on a board we can just do
the mux config once, configuring McBSP1 and MMC/SDIO at the same time?
>> In .dtsi file of the SoC:
>>
>> control_devconf0: pinmux@48002274 {
>> compatible = "pinctrl-single";
>> reg = <0x48002274 4>; /* Single register */
>> #address-cells = <1>;
>> #size-cells = <0>;
>> pinctrl-single,register-width = <32>;
>> pinctrl-single,function-mask = <0x5F>;
>> };
>
> The pinctrl-single,function-mask is for all the registers in the range,
> we also need something to specify the device specific mux bits.
Yes, I understand that.
I think this all depends if we want to change the mux configurations runtime,
on the fly as well. If it is only done once at boot time why not just set up
the register (mux) as the board design dictates?
>> In the .dts file of the board which needs to change the CLKR/FSR configuration:
>>
>> &control_devconf0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&mcbsp1_pins>;
>>
>> mcbsp1_pins: pinmux_mcbsp1_pins {
>> pinctrl-single,pins = <0x00 0x18>; /* CLKR/FSR from CLKX/FSX
>> * pin */
>> };
>>
>> };
>
> I think adding support for one-bit-per-mux would require adding something
> like this for the binding:
>
> mcbsp1_pins: pinmux_mcbsp1_pins {
> /* offset bits mask */
> pinctrl-single,bits = <0x00 0x18 0x18>;
> };
>
> As otherwise you would not know which bits to clear for alternative
> named modes. Or got any better ideas?
I was also thought that this type of feature might be useful at some point in
pinctrl.
However if we have static mux configuration on a boards vendors can set up the
mux for their devices using the currently available bindings.
--
Péter
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