On 09/01/2011 08:46 PM, Kevin Hilman wrote:
javier Martin<javier.martin@xxxxxxxxxxxxxxxxx> writes:
Hi Kevin,
thanks for your help.
CPU is staying in C0 probably because UARTs are not being idled, so SoC
cannot hit deeper idle states. Try the following at the command line to
to enable UART idle timeouts, so the SoC can attempt idle after the
timeout period
# UART timeouts: omap-serial (4th UART only on OMAP36xx and OMAP4)
echo 5> /sys/devices/platform/omap/omap_uart.0/sleep_timeout
echo 5> /sys/devices/platform/omap/omap_uart.1/sleep_timeout
echo 5> /sys/devices/platform/omap/omap_uart.2/sleep_timeout
echo 5> /sys/devices/platform/omap/omap_uart.3/sleep_timeout
After 5 seconds of inactivity on the UARTs, you should see the SoC
hitting deeper C-states.
I've tried that but it still doesn't hit any C-state deeper than 0.
I'll try the same test using your pm branch you pointed me out and
post the results.
The CPUidle stuff works in mainline (after allowing UARTs to idle).
Other usual things to check that display is off (echo 1 >
/sys/class/graphics/fb0/blank) and no cable to musb/otg port.
Haven't tried myself with recent kernel but does EHCI and hub on XM let
to idle cpu at all? At least on one board having on-board hub I had to
disable or unload ehci module in order to hit the retention.
--
Jarkko
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