Re: cpuidle status in mainline for Beagleboard xM

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javier Martin <javier.martin@xxxxxxxxxxxxxxxxx> writes:

> Hi Kevin,
> thanks for your help.
>
>> CPU is staying in C0 probably because UARTs are not being idled, so SoC
>> cannot hit deeper idle states.  Try the following at the command line to
>> to enable UART idle timeouts, so the SoC can attempt idle after the
>> timeout period
>>
>> # UART timeouts: omap-serial (4th UART only on OMAP36xx and OMAP4)
>> echo 5 > /sys/devices/platform/omap/omap_uart.0/sleep_timeout
>> echo 5 > /sys/devices/platform/omap/omap_uart.1/sleep_timeout
>> echo 5 > /sys/devices/platform/omap/omap_uart.2/sleep_timeout
>> echo 5 > /sys/devices/platform/omap/omap_uart.3/sleep_timeout
>>
>> After 5 seconds of inactivity on the UARTs, you should see the SoC
>> hitting deeper C-states.
>
> I've tried that but it still doesn't hit any C-state deeper than 0.
> I'll try the same test using your pm branch you pointed me out and
> post the results.
>

The CPUidle stuff works in mainline (after allowing UARTs to idle).

You only need my pm-wip/cpufreq branch for testing CPUfreq.

Kevin

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