On Tue, 1 Feb 2011, Santosh Shilimkar wrote: > > -----Original Message----- > > From: Paul Walmsley [mailto:paul@xxxxxxxxx] > > Sent: Tuesday, February 01, 2011 4:44 AM > > > > What does the hardware do when the powerdomain is programmed to > > INACTIVE? > > Does it actually force the clockdomains idle? > > No. It doesn't force it. The power domain to hit INACTIVE, the > clockdomain within the power domain needs to idle and it is > still a prerequisite. With INACTIVE being programmed, we could > issue a sleep transition. > > PD_ON: > No power transition, only clocks are gated. Power domain stays ON. > > PD_INA: > Power domain transitions to INACTIVE state. All logic and > memory stay powered. This state allows for a voltage > sleep transition. Okay. So programming an OMAP4 powerdomain to INACTIVE is equivalent to programming an OMAP3 powerdomain to ON with the PRM_VOLTCTRL.AUTO_SLEEP bit to 1? Are there any other dependencies with the PRM_VOLTCTRL_AUTO_CTRL_VDD* registers, e.g., does the appropriate VDD bitfield there need to be set to 0x1 also to allow the sleep transition to occur? - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
