Re: Open issues after 2.6.38 merge window

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On Mon, 17 Jan 2011, Russell King wrote:

> On Mon, Jan 17, 2011 at 02:00:17PM -0700, Paul Walmsley wrote:
> > On Mon, 17 Jan 2011, Russell King wrote:
> > > On Mon, Jan 17, 2011 at 01:31:47PM -0700, Paul Walmsley wrote:
> > > > 
> > > > OMAP15xx uses the MPU timer for its clocksource, since OMAP15xx doesn't 
> > > > have GPTIMERs or the 32k sync timer, and the MPU timer code in 
> > > > mach-omap1/time.c wasn't updated for sched_clock() support.
> > > > 
> > > > Adding an init_fixed_sched_clock() into omap_init_clocksource() should 
> > > > fix the boot on OMAP15xx/7xx.
> > > 
> > > No, it needs fixing properly.  There's no reason the gpt clocksource
> > > can't be used for sched_clock.
> > 
> > There's a very good reason why it can't on OMAP15xx/7xx.  GPTIMER/DMTIMER 
> > IP blocks are only present on OMAP1610 and later[1].  Nor is a 
> > SYNCTIMER_32K IP block present on OMAP15xx/7xx[2].
> 
> Yes I realise that.  That doesn't negate what I said though.  Let me
> show you how to do it:

...

> Both a GPT _and_ 32K sched_clock implementation together, selectable
> at runtime or build time depending on what is selected.  I'll give you
> that it isn't nice code, but it does what's required.

Right.  I agree that it is possible to support both GPTIMER and 32KiHz 
clocksources at runtime.  But there should be a third case in that code 
also, a case for the OMAP1 MPU Timer IP blocks.  

Of course, it would be technically possible to define "GPT"/"GPTIMER" to 
mean "MPU Timer" on OMAP15xx/OMAP7xx.  However, later OMAP1 chips contain 
all three of the above-mentioned timer IP blocks: GPTIMERs[1], a 
SYNCTIMER_32K[2], and the MPU Timers[3].  Each of these timers also has 
distinct power, interconnect, and register access properties.  So it seems 
less confusing to keep the MPU Timer case distinct from the GPTIMER/GPT 
case.


- Paul


1. OMAP1611/12 Multimedia Processor Technical Reference Manual [SWPU066B],
   section 13.5, "Dual-Mode Timer"

2. OMAP1611/12 Multimedia Processor Technical Reference Manual [SWPU066B],
   section 13.6, "32-kHz Synchronized Timer"

3. OMAP1611/12 Multimedia Processor Technical Reference Manual [SWPU066B],
   section 13.4, "OMAP3.2 Operating System Timer"
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