Re: [PATCH v5 02/17] OMAP2430: hwmod data: add DSS DISPC RFBI VENC

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Hello Sumit, Senthilvadivu,

here are some initial comments based on a preliminary review.

On Fri, 7 Jan 2011, Sumit Semwal wrote:

> From: Senthilvadivu Guruswamy <svadivu@xxxxxx>
> 
> Hwmod needs database of all IPs in a system. This patch generates the hwmod
> database for OMAP2430 Display Sub System. Since DSS is also considered as an
> IP as DISPC, RFBI, name it as dss_dss.
> 
> Signed-off-by: Senthilvadivu Guruswamy <svadivu@xxxxxx>
> Acked-by: Benoit Cousson <b-cousson@xxxxxx>
> ---
>  arch/arm/mach-omap2/omap_hwmod_2430_data.c |  282 ++++++++++++++++++++++++++++
>  1 files changed, 282 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
> index 8ecfbcd..b06eeea 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
> @@ -38,6 +38,10 @@ static struct omap_hwmod omap2430_mpu_hwmod;
>  static struct omap_hwmod omap2430_iva_hwmod;
>  static struct omap_hwmod omap2430_l3_main_hwmod;
>  static struct omap_hwmod omap2430_l4_core_hwmod;
> +static struct omap_hwmod omap2430_dss_dss_hwmod;
> +static struct omap_hwmod omap2430_dss_dispc_hwmod;
> +static struct omap_hwmod omap2430_dss_rfbi_hwmod;
> +static struct omap_hwmod omap2430_dss_venc_hwmod;

What about the SDI module?  According to the OMAP2430 TRM Rev. Z 
[SWPU090Z] Figure 15-32 "Display Subsystem Integration", there is an SDI 
module here also.

>  static struct omap_hwmod omap2430_wd_timer2_hwmod;
>  static struct omap_hwmod omap2430_gpio1_hwmod;
>  static struct omap_hwmod omap2430_gpio2_hwmod;
> @@ -65,6 +69,13 @@ static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
>  	&omap2430_mpu__l3_main,
>  };
>  
> +/* DSS -> l3 */
> +static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
> +	.master		= &omap2430_dss_dss_hwmod,
> +	.slave		= &omap2430_l3_main_hwmod,
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
>  /* Master interfaces on the L3 interconnect */
>  static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
>  	&omap2430_l3_main__l4_core,
> @@ -469,6 +480,271 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
>  	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
>  };
>  
> +/*
> + * 'dss' class
> + * display sub-system
> + */
> +
> +static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
> +	.rev_offs	= 0x0000,
> +	.sysc_offs	= 0x0010,
> +	.syss_offs	= 0x0014,
> +	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
> +	.sysc_fields	= &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class omap2430_dss_hwmod_class = {
> +	.name = "dss",
> +	.sysc = &omap2430_dss_sysc,
> +};
> +
> +/* dss */
> +static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
> +	{ .irq = 25 },
> +};
> +static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
> +	{ .name = "dispc", .dma_req = 5 },
> +};
> +
> +/* dss */
> +/* dss master ports */
> +static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
> +	&omap2430_dss__l3,
> +};
> +
> +static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
> +	{
> +		.pa_start	= 0x48050000,
> +		.pa_end		= 0x480503FF,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_core -> dss */
> +static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
> +	.master		= &omap2430_l4_core_hwmod,
> +	.slave		= &omap2430_dss_dss_hwmod,
> +	.clk		= "dss_ick",
> +	.addr		= omap2430_dss_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap2430_dss_addrs),

This struct omap_hwmod_ocp_if record is missing firewall data.
Please add.  See, for example, "omap3_l4_core__i2c1" in
mach-omap2/omap_hwmod_3xxx_data.c, for an example of how to add
this data.  Much of the data that you need can be found in Table
5-108 "L4 Core Memory Space Mapping" of the OMAP2430 TRM Rev. Z
[SWPU090Z].

> +	.user		= OCP_USER_MPU,

Unless there's some reason why the SDMA can't access this module,
the .user field should be set to OCP_USER_MPU | OCP_USER_SDMA.

> +};
> +
> +/* dss slave ports */
> +static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
> +	&omap2430_l4_core__dss,
> +};
> +
> +static struct omap_hwmod_opt_clk dss_opt_clks[] = {
> +	{ .role = "tv_clk", .clk = "dss_54m_fck" },
> +	{ .role = "sys_clk", .clk = "dss2_fck" },
> +};
> +
> +static struct omap_hwmod omap2430_dss_dss_hwmod = {
> +	.name		= "dss_dss",
> +	.class		= &omap2430_dss_hwmod_class,
> +	.main_clk	= "dss1_fck", /* instead of dss_fck */
> +	.mpu_irqs	= omap2430_dss_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(omap2430_dss_irqs),
> +	.sdma_reqs	= omap2430_dss_sdma_chs,
> +	.sdma_reqs_cnt	= ARRAY_SIZE(omap2430_dss_sdma_chs),
> +

Please remove this extra blank line.

> +	.prcm		= {
> +		.omap2 = {
> +			.prcm_reg_id = 1,
> +			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
> +			.module_offs = CORE_MOD,
> +			.idlest_reg_id = 1,
> +			.idlest_idle_bit = OMAP24XX_ST_DSS_SHIFT,

According to Table 4-219 "CM_IDLEST_DSS" of the OMAP2430 TRM Rev. Z 
[SWPU090Z], the DSS has both a target idle and an initiator standby status 
bit.  Please update the fields here accordingly.  You may also need to add 
a patch to your series to update the mach-omap2/cm-regbits-24xx.h file.

> +		},
> +	},
> +	.opt_clks	= dss_opt_clks,
> +	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
> +	.slaves		= omap2430_dss_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap2430_dss_slaves),
> +	.masters	= omap2430_dss_masters,
> +	.masters_cnt	= ARRAY_SIZE(omap2430_dss_masters),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
> +	.flags		= HWMOD_NO_IDLEST,

2430 DSS has a target idle status bit, so this flag shouldn't be set.

> +};
> +
> +/*
> + * 'dispc' class
> + * display controller
> + */
> +
> +static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
> +	.rev_offs	= 0x0000,
> +	.sysc_offs	= 0x0010,
> +	.syss_offs	= 0x0014,
> +	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
> +			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
> +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> +			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
> +	.sysc_fields	= &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
> +	.name = "dispc",
> +	.sysc = &omap2430_dispc_sysc,
> +};
> +
> +static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
> +	{
> +		.pa_start	= 0x48050400,
> +		.pa_end		= 0x480507FF,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_core -> dss_dispc */
> +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
> +	.master		= &omap2430_l4_core_hwmod,
> +	.slave		= &omap2430_dss_dispc_hwmod,

It appears, from reading Table 5-108 "L4 Core Memory Space
Mapping" of the OMAP2430 TRM Rev. Z [SWPU090Z], that there is
only one L4 CORE port for the entire DSS.  However, the struct
omap_hwmod_ocp_if data here claims that this submodule has its
own L4 CORE port. Shouldn't this struct omap_hwmod_ocp_if record
have omap2430_dss_dss_hwmod as its .master ?  See also Figure
15-33 "Display Subsystem Full Schematic".

> +	.clk		= "dss_ick",
> +	.addr		= omap2430_dss_dispc_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap2430_dss_dispc_addrs),

This struct omap_hwmod_ocp_if record is missing firewall data.
Please add.  See, for example, "omap3_l4_core__i2c1" in
mach-omap2/omap_hwmod_3xxx_data.c, for an example of how to add
this data.  Much of the data that you need can be found in Table
5-108 "L4 Core Memory Space Mapping" of the OMAP2430 TRM Rev. Z
[SWPU090Z].

> +	.user		= OCP_USER_MPU,

Unless there's some reason why the SDMA can't access this module,
the .user field should be set to OCP_USER_MPU | OCP_USER_SDMA.

> +};
> +
> +/* dss_dispc slave ports */
> +static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
> +	&omap2430_l4_core__dss_dispc,
> +};
> +
> +static struct omap_hwmod omap2430_dss_dispc_hwmod = {
> +	.name		= "dss_dispc",
> +	.class		= &omap2430_dispc_hwmod_class,
> +	.main_clk	= "dss1_fck",
> +	.prcm		= {
> +		.omap2 = {
> +			.prcm_reg_id = 1,
> +			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
> +			.module_offs = CORE_MOD,
> +			.idlest_reg_id = 1,
> +			.idlest_idle_bit = OMAP24XX_ST_DSS_SHIFT,

According to Table 4-219 "CM_IDLEST_DSS" of the OMAP2430 TRM Rev. Z
[SWPU090Z], the DSS has both a target idle and an initiator standby status
bit.  Please update the fields here accordingly.  You may also need to add
a patch to your series to update the mach-omap2/cm-regbits-24xx.h file.

> +		},
> +	},
> +	.slaves		= omap2430_dss_dispc_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap2430_dss_dispc_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
> +	.flags		= HWMOD_NO_IDLEST,

2430 DSS has a target idle status bit, so this flag shouldn't be set.

> +};
> +
> +/*
> + * 'rfbi' class
> + * remote frame buffer interface
> + */
> +
> +static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
> +	.rev_offs	= 0x0000,
> +	.sysc_offs	= 0x0010,
> +	.syss_offs	= 0x0014,
> +	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
> +			   SYSC_HAS_AUTOIDLE),
> +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> +	.sysc_fields	= &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
> +	.name = "rfbi",
> +	.sysc = &omap2430_rfbi_sysc,
> +};
> +
> +static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
> +	{
> +		.pa_start	= 0x48050800,
> +		.pa_end		= 0x48050BFF,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_core -> dss_rfbi */
> +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
> +	.master		= &omap2430_l4_core_hwmod,
> +	.slave		= &omap2430_dss_rfbi_hwmod,

It appears, from reading Table 5-108 "L4 Core Memory Space
Mapping" of the OMAP2430 TRM Rev. Z [SWPU090Z], that there is
only one L4 CORE port for the entire DSS.  However, the struct
omap_hwmod_ocp_if data here claims that this submodule has its
own L4 CORE port. Shouldn't this struct omap_hwmod_ocp_if record
have omap2430_dss_dss_hwmod as its .master ?  See also Figure
15-33 "Display Subsystem Full Schematic".

> +	.clk		= "dss_ick",
> +	.addr		= omap2430_dss_rfbi_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap2430_dss_rfbi_addrs),

This struct omap_hwmod_ocp_if record is missing firewall data.
Please add.  See, for example, "omap3_l4_core__i2c1" in
mach-omap2/omap_hwmod_3xxx_data.c, for an example of how to add
this data.  Much of the data that you need can be found in Table
5-108 "L4 Core Memory Space Mapping" of the OMAP2430 TRM Rev. Z
[SWPU090Z].

> +	.user		= OCP_USER_MPU,

Unless there's some reason why the SDMA can't access this module,
the .user field should be set to OCP_USER_MPU | OCP_USER_SDMA.

> +};
> +
> +/* dss_rfbi slave ports */
> +static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
> +	&omap2430_l4_core__dss_rfbi,
> +};
> +
> +static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
> +	.name		= "dss_rfbi",
> +	.class		= &omap2430_rfbi_hwmod_class,
> +	.main_clk	= "dss1_fck",
> +	.prcm		= {
> +		.omap2 = {
> +			.prcm_reg_id = 1,
> +			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
> +			.module_offs = CORE_MOD,
> +			.idlest_reg_id = 1,
> +			.idlest_idle_bit = OMAP24XX_ST_DSS_SHIFT,

See the above comments regarding these .prcm sections.  Since this module 
doesn't have anything to do with the L3 interface, it shouldn't have an 
.idlest_stdby_bit, but the idlest_idle_bit should presumably be 
OMAP2430_ST_DSS_IDLE_SHIFT.

> +		},
> +	},
> +	.slaves		= omap2430_dss_rfbi_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap2430_dss_rfbi_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
> +	.flags		= HWMOD_NO_IDLEST,

2430 DSS has a target idle status bit, so this flag shouldn't be set.

> +};
> +
> +/*
> + * 'venc' class
> + * video encoder
> + */
> +
> +static struct omap_hwmod_class omap2430_venc_hwmod_class = {
> +	.name = "venc",
> +};
> +
> +/* dss_venc */
> +static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
> +	{
> +		.pa_start	= 0x48050C00,
> +		.pa_end		= 0x48050FFF,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_core -> dss_venc */
> +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
> +	.master		= &omap2430_l4_core_hwmod,
> +	.slave		= &omap2430_dss_venc_hwmod,

It appears, from reading Table 5-108 "L4 Core Memory Space
Mapping" of the OMAP2430 TRM Rev. Z [SWPU090Z], that there is
only one L4 CORE port for the entire DSS.  However, the struct
omap_hwmod_ocp_if data here claims that this submodule has its
own L4 CORE port. Shouldn't this struct omap_hwmod_ocp_if record
have omap2430_dss_dss_hwmod as its .master ?  See also Figure
15-33 "Display Subsystem Full Schematic".

> +	.clk		= "dss_54m_fck",
> +	.addr		= omap2430_dss_venc_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap2430_dss_venc_addrs),

This struct omap_hwmod_ocp_if record is missing firewall data.
Please add.  See, for example, "omap3_l4_core__i2c1" in
mach-omap2/omap_hwmod_3xxx_data.c, for an example of how to add
this data.  Much of the data that you need can be found in Table
5-108 "L4 Core Memory Space Mapping" of the OMAP2430 TRM Rev. Z
[SWPU090Z].

> +	.user		= OCP_USER_MPU,

Unless there's some reason why the SDMA can't access this module,
the .user field should be set to OCP_USER_MPU | OCP_USER_SDMA.

> +};
> +
> +/* dss_venc slave ports */
> +static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
> +	&omap2430_l4_core__dss_venc,
> +};
> +
> +static struct omap_hwmod omap2430_dss_venc_hwmod = {
> +	.name		= "dss_venc",
> +	.class		= &omap2430_venc_hwmod_class,
> +	.main_clk	= "dss1_fck",
> +	.prcm		= {
> +		.omap2 = {
> +			.prcm_reg_id = 1,
> +			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
> +			.module_offs = CORE_MOD,
> +			.idlest_reg_id = 1,
> +			.idlest_idle_bit = OMAP24XX_ST_DSS_SHIFT,

See the above comments regarding these .prcm sections.  Since this module
doesn't have anything to do with the L3 interface, it shouldn't have an   
.idlest_stdby_bit, but the idlest_idle_bit should presumably be
OMAP2430_ST_DSS_IDLE_SHIFT.

> +		},
> +	},
> +	.slaves		= omap2430_dss_venc_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap2430_dss_venc_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
> +	.flags		= HWMOD_NO_IDLEST,

2430 DSS has a target idle status bit, so this flag shouldn't be set.

> +};
> +
>  /* I2C common */
>  static struct omap_hwmod_class_sysconfig i2c_sysc = {
>  	.rev_offs	= 0x00,
> @@ -929,6 +1205,12 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
>  	&omap2430_uart1_hwmod,
>  	&omap2430_uart2_hwmod,
>  	&omap2430_uart3_hwmod,
> +	/* dss class */
> +	&omap2430_dss_dss_hwmod,
> +	&omap2430_dss_dispc_hwmod,
> +	&omap2430_dss_rfbi_hwmod,
> +	&omap2430_dss_venc_hwmod,
> +	/* i2c class */
>  	&omap2430_i2c1_hwmod,
>  	&omap2430_i2c2_hwmod,
>  
> -- 
> 1.7.0.4
> 
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- Paul
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