On Mon, 3 Jan 2011, Hemant Pedanekar wrote: > Note2: The optimized irq macro for omap3 skips checking the 4th irq status > register but this needs to be added for TI816X (interrupts 96 to 127). > Presently, only the multi-omap irq macro (unoptimized) is updated to check the > 4th status register. Sounds like you should either add an #ifdef CONFIG_ARCH_OMAPTI816X (or whatever macro name you use) to the optimized version to check the fourth ISR. Either that, or add code to force a MULTI_OMAP build when compiling for this chip. Otherwise if someone builds an "optimized", non-multi-OMAP kernel for this chip, they'll be pretty surprised when it misses interrupts from that fourth bank. - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
