Santosh Shilimkar wrote, on 12/20/2010 12:59 AM:
[..]
index 3fbd1e5..cc3507b 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -45,6 +45,8 @@
#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
#define SRAM_BASE_P 0x40200000
#define CONTROL_STAT 0x480022F0
+#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
+ + OMAP36XX_CONTROL_MEM_RTA_CTRL)
Just a clarification. This register is not part of HW SAR SCM
Registers, right ?
Right.
[..]
--
Regards,
Nishanth Menon
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