Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue

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"Sripathy, Vishwanath" <vishwanath.bs@xxxxxx> writes:

>> All that being said, why is the voltage level being programmed here?
>> 
>> It seems to me that all of this errata handling should be
>> self-contained in the voltage layer.
>
> I am not sure if entire errata can be contained in voltage
> layer. This is because we are performing DVFS operation in CPU Idle
> path which involves both Frequency and Voltage scaling. So currently
> this has been done in resource34xx.c where DVFS is implemented.

What I mean is that there seems to be no good reason to be calling
these from pm34xx.c, they should be called where voltage scaling is
done.

Kevin

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