* Mika Westerberg <ext-mika.1.westerberg@xxxxxxxxx> [100503 05:52]:
> If we are softbooting another kernel using kexec, DMA controller state is not
> known when we are performing omap_init_dma(). It is possible that some DMA
> channels are already active. For example after kexec we get:
>
> <4>IRQ 0020 for non-allocated DMAchannel 5
> <4>IRQ 0020 for non-allocated DMAchannel 5
> <4>IRQ 0020 for non-allocated DMAchannel 5
> <4>IRQ 0020 for non-allocated DMAchannel 5
> <4>IRQ 0020 for non-allocated DMAchannel 5
>
> To prevent any weird things happening, we perform soft reset for the controller
> and disable all per channel interrupts.
>
> Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@xxxxxxxxx>
> ---
> arch/arm/plat-omap/dma.c | 32 ++++++++++++++++++++++++++++++++
> arch/arm/plat-omap/include/plat/dma.h | 4 ++++
> 2 files changed, 36 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
> index 1d95996..24cbb97 100644
> --- a/arch/arm/plat-omap/dma.c
> +++ b/arch/arm/plat-omap/dma.c
> @@ -2024,6 +2024,31 @@ void omap_dma_global_context_restore(void)
>
> /*----------------------------------------------------------------------------*/
>
> +/**
> + * omap_dma_reset() - perform software reset for the DMA controller
> + */
> +static void omap_dma_reset(void)
> +{
> + u32 v;
> +
> + if (cpu_class_is_omap1())
> + return;
> +
> + v = dma_read(OCP_SYSCONFIG);
> + v |= 0x2; /* software reset */
> + dma_write(v, OCP_SYSCONFIG);
> +
> + /* wait until reset is complete */
> + while ((dma_read(SYSSTATUS) & 0x1) == 0)
> + cpu_relax();
This reset part seems to be mach-omap2 specific.
> + /* disable per channel interrupts */
> + dma_write(0, IRQENABLE_L0);
> + dma_write(0, IRQENABLE_L1);
> + dma_write(0, IRQENABLE_L2);
> + dma_write(0, IRQENABLE_L3);
> +}
For a minimal fix, how about just disable the interrupt in omap_clear_dma()?
We are already calling that from omap_init_dma().
Regards,
Tony
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