> /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
> err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address,
> R_SEQ_ADD_A2S);
>
> I am not an expert on the twl4030, but I am guessing that enables
> sleep.
This PMIC at COLD reset uses internal OTP mask rom defaults for any sequencing needs.
After power up SW can programming in new sequences into PMIC internal SRAM. This flexibility is needed as the PMIC can control several different optional board level hook ups. To really program the PMIC correctly you have to know something about the boards requirements.
The above is telling the PMIC the address of the sequence to execute for an omap3 soc-level sleep event. The sequence is made up of internal write and delay commands.
If someone cares to understand, the PMIC memory can be dumped and the sequences examined. But as I said some of these sequences 'should' have a board-to-pmic hook up dependency. Not all sequences will make sense for every board design. Generally to get OFF modes done correctly and optimized this level of detail needs to be handled.
Using trial and error maybe you can arrive with something which doesn't crash... but it might not really be doing the right thing.
Regards,
Richard W.
��.n��������+%������w��{.n�����{�������ܨ}���Ơz�j:+v�����w����ޙ��&�)ߡ�a����z�ޗ���ݢj��w�f
