Re: OMAP35XX SGX Driver and hwmod

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Hello,

On Tue, Aug 23, 2016 at 6:41 PM, Suman Anna <s-anna@xxxxxx> wrote:
> On 08/19/2016 06:39 PM, Tony Lindgren wrote:
>> * Adam Ford <aford173@xxxxxxxxx> [160818 12:20]:
>>>
>>> Does anyone have any suggestions on the best way to approach?
>>
>> In the long run we should have drivers/drm just manage these
>> devices using PM runtime and then just load firmware for the
>> sgx if available. Not sure what all needs to change for that
>> to happen though..
>
> Unfortunately, the omap_hwmod code alone can't deal with PRCM reset
> lines, so you would still require the drivers to have to call some API
> for managing the resets, or if it is one-time boot-time setup thing, can
> do what was done for DRA7 PCIe (see commit 1c96bee4df19).
I did look to omap35xx trm and it's stated thas for sgx reset is necessary to:
The SGX subsystem has its own reset domain. Global reset of the SGX is
performed by activating the
SGX_RST signal in the SGX_RST domain. Software controls the release of
SGX_RST using the
PRCM.RM_RSTCTRL_SGX[0] SGX_RST bit.

But I cannot find RSTCTRL_SGX register nor SGX_RST bit in whole trm.
Am I missing something?
I have compiled pvr driver (with few small tweaks) agains 4.9 kernel
and also did look to Adam's patch [0]
I would like to implement what you suggested (similar to commit:
1c96bee4df19). Thanks.
>
> regards
> Suman

BR,

marek
>
>>
>> Also please check what the n900 and pandora/pyra people have
>> done to get sgx working, there may be something usaable there.
>>
>> Regards,
>>
>> Tony
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>
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